Assembly and Packaging Development Engineer
- indie Semiconductor Inc.
- Aliso Viejo, California
- Full Time
We are seeking an experienced Package Development Engineer to lead the design and development of advanced IC packages for power, analog, mixed-signal, high-speed RF, and digital applications. This role is pivotal in ensuring packaging solutions meet stringent requirements for performance, reliability, cost, and manufacturability.
Responsibilities
Lead the design and development of packaging solutions for new and existing ICs, ensuring compliance with power, thermal, mechanical, signal integrity, testability, and reliability requirements.
Evaluate packaging technologies and suppliers globally to select optimal solutions based on technical performance, cost, and risk.
Drive internal technical reviews, roadmap alignment, supplier evaluations, audits, and BOM selection.
Align packaging strategies with internal product roadmaps, resource and cost constraints, supplier capabilities, and customer requirements.
Collaborate with Design, Product, Foundry, and Test teams to define packaging requirements and guide silicon and hardware design using DFM and simulation results.
Advise on silicon metallization schemes, signal/power routing, bump/ball layouts, and netlist optimization to ensure efficient package integration.
Define and manage package qualification and reliability plans; troubleshoot and resolve reliability issues from field or product qualification failures.
Support root cause analysis (e.g., 8D) and corrective actions (CAR) for supplier-related quality issues and process excursions.
Provide input to PFMEAs and help identify critical-to-quality characteristics to support a zero-defect manufacturing strategy.
Maintain documentation, specifications, and procedures related to package design and process control.
Assess and mitigate the impact of supplier PCNs and drive cost reduction and yield improvement initiatives.
Support development of alternate sources and help negotiate with packaging suppliers.
Key Qualifications
10+ years of experience in IC package design for high-power and high-speed RF/digital applications.
Proven experience in multi-chip and multi-layer package design, including aQFN, WLCSP, WLBGA, FCCSP, FCBGA, MISBGA, Embedded Die, MCM, and SiP.
In-depth knowledge of flip-chip substrate and wirebond lead frame design, including RDL, bumping, copper pillars, and signal/power integrity considerations.
Solid understanding of package failure mechanisms and reliability models.
Hands-on experience with mechanical, electrical, and thermal simulation tools (e.g., Flotherm, Icepak).
Familiarity with backend silicon layout tools such as Cadence, AutoCAD, APD, or SiP.
Exposure to assembly equipment, substrate and lead-frame processes, and package process integration.
Strong analytical and root-cause problem-solving skills.
Experience collaborating with and negotiating technical and commercial terms with suppliers.